An issue that is crucial to the performance of the PCM system is the encoder's clock frequency. The clock tells the PCM encoder when to sample and this must be at least twice the message frequency to avoid aliasing (or, if the message contains more than one sinewave, at least twice its highest frequency).

Another important PCM performance issue relates to the difference between the sample voltage and the quantisation levels that it is compared to. To explain, most sampled voltages will not be the same as any of the quantisation levels. As mentioned above, the PCM Encoder assigns to the sample the quantisation level that is closest to it. However, in the process, the original sample's value is lost and the difference is known as quantisation error. Importantly, the error is reproduced when the PCM data is decoded by the receiver because there is no way for the receiver to know what the original sample voltage was. The size of the error is affected by the number of quantisation levels. The more quantisation levels there are (for a given range of sample voltages) the closer they are together. This means that the difference between the quantisation levels and the samples is smaller and so the error is lower.

Fig.1 shows an example of three frames of a PCM Encoder module's output data (each bit is shown as both a 0 and a 1 because it could be either) together with its clock input and its FS output.